Pin Diagram and Pin description of 8085

8085 is a 40 pin IC, The signals from the pins can be grouped as follows

1. Power supply and clock signals
2. Address bus
3. Data bus
4. Control and status signals
5. Interrupts and externally initiated signals
6. Serial I/O ports

1. Power supply and Clock frequency signals:

Vcc: + 5 volt power supply
Vss: Ground
X1, X2 : Crystal or R/C network or LC network connections to set the frequency of internal clock generator. The frequency is internally divided by two. Since the basic operating timing frequency is 3 MHz, a 6 MHz crystal is connected externally. CLK (output)-Clock Output is used as the system clock for peripheral and devices interfaced with the microprocessor.

2. Address Bus:

A8 - A15: (output; 3-state)
It carries the most significant 8 bits of the memory address or the 8 bits of the I/O address.

3. Data bus:

AD0 - AD7 (input/output; 3-state)
  • These multiplexed set of lines used to carry the lower order 8 bit address as well as data bus.
  • During the opcode fetch operation, in the first clock cycle, the lines deliver the lower order address A0 - A7.
  • In the subsequent IO / memory, read / write clock cycle the lines are used as data bus.
  • The CPU may read or write out data through these lines.

4. Control and Status signals:

ALE (output) - Address Latch Enable.
  • It is an output signal used to give information of AD0-AD7 contents.
  • It is a positive going pulse generated when a new operation is started by uP.
  • When pulse goes high it indicates that AD0-AD7 are address.
  • When it is low it indicates that the contents are data.

RD (output 3-state, active low)
  • Read memory or IO device.
  • This indicates that the selected memory location or I/O device is to be read and that the data bus is ready for accepting data from the memory or I/O device

WR (output 3-state, active low)
  • Write memory or IO device.
  • This indicates that the data on the data bus is to be written into the selected memory location or I/O device.

  • IO/M (output) - Select memory or an IO device.
    • This status signal indicates that the read / write operation relates to whether the memory or I/O device.
    • It goes high to indicate an I/O operation.
    • It goes low for memory operations.

    5. Status Signals:

    S1: S2:
    It is used to know the type of current operation of the microprocessor.
    011Opcode fetch
    010Memory read
    001Memory write
    110I/O read
    101I/O write
    110Interrupt acknowledge

    6. Interrupts and Externally initiated operations:

  • They are the signals initiated by an external device to request the microprocessor to do a particular task or work.
  • There are five hardware interrupts called,
  • TRAP
    RST 7.5
    RST 6.5
    RST 5.5

  • On receipt of an interrupt, the microprocessor acknowledges the interrupt by the active low INTA (Interrupt Acknowledge) signal.

  • Reset In (input, active low)
  • This signal is used to reset the microprocessor.
  • The program counter inside the microprocessor is set to zero.
  • The buses are tri-stated.
  • Reset Out (Output)
  • It indicates CPU is being reset.
  • Used to reset all the connected devices when the microprocessor is reset.

  • 7. Direct Memory Access (DMA): Tri state devices:

  • When 2 or more devices are connected to a common bus, to prevent the devices from interfering with each other, the tristate gates are used to disconnect all devices except the one that is communicating at a given instant.
  • The CPU controls the data transfer operation between memory and I/O device. Direct Memory Access operation is used for large volume data transfer between memory and an I/O device directly.
  • The CPU is disabled by tri-stating its buses and the transfer is effected directly by external control circuits.
  • HOLD signal is generated by the DMA controller circuit. On receipt of this signal, the microprocessor acknowledges the request by sending out HLDA signal and leaves out the control of the buses. After the HLDA signal the DMA controller starts the direct transfer of data.

  • READY (input)
  • Memory and I/O devices will have slower response compared to microprocessors.
  • Before completing the present job such a slow peripheral may not be able to handle further data or control signal from CPU.
  • The processor sets the READY signal after completing the present job to access the data.
  • The microprocessor enters into WAIT state while the READY pin is disabled.

  • 8. Single Bit Serial I/O ports:

    SID (input) Serial input data line
    SOD (output) Serial output data line
    These signals are used for serial communication.