Block Diagram of 8237

8237 Internal Registers

CAR

---

• The current address register holds a 16-bit memory address used for the DMA transfer.
• each channel has its own current address register for this purpose.
• When a byte of data is transferred during a DMA operation, CAR is either incrementedor decremented. depending on how it is programmed



CWCR

---

• The current word count register programs a channel for the number of bytes to transferred during a DMA action.



CR

---

• The command register programs the operation of the 8237 DMA controller.
• The register uses bit position 0 to select the memory-to-memory DMA transfer mode.
  1. Memory-to-memory DMA transfers use DMA channel
  2. DMA channel 0 to hold the source address
  3. DMA channel 1 holds the destination address




BA and BWC

---

• The base address (BA) and base word count (BWC) registers are used when auto-initialization is selected for a channel.
• In auto-initialization mode, these registers are used to reload the CAR and CWCR after the DMA action is completed.



MR

---

• The mode register programs the mode of operation for a channel.
• Each channel has its own mode register as selected by bit positions 1 and 0.
  1. Remaining bits of the mode register select operation, auto-initialization, increment/decrement, and mode for the channel




BR

---

• The bus request register is used to request a DMA transfer via software.
  1. very useful in memory-to-memory transfers, where an external signal is not available to begin the DMA transfer




MRSR

---

• The mask register set/reset sets or clears the channel mask.
  1. if the mask is set, the channel is disabled
  2. the RESET signal sets all channel masksto disable them




MSR

---

• The mask register clears or sets all ofthe masks with one command instead of individual channels, as with the MRSR.




SR

---

• The status register shows status of each DMA channel. The TC bits indicate if the channel has reached its terminal count (transferred all its bytes).
• When the terminal count is reached, the DMA transfer is terminated for most modesof operation.
• The request bits indicate whether the DREQ input for a given channel is active.

8237 Software Commands

Master clear

---

Acts exactly the same as the RESET signal to the 8237. As with the RESET signal, this command disables all channels



Clear mask register

---

Enables all four DMA channels.



Clear the first/last flip-flop

---

Clears the first/last (F/L) flip-flop within 8237. The F/L flip-flop selects which byte (low or high order) is read/written in the current address and current count registers. if F/L = 0, the low-order byte is selected if F/L = 1, the high-order byte is selected Any read or write to the address or count register automatically toggles the F/L flip-flop.